hal: ra: Fix pll clock config get from dts #40
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The new update of dts in device tree make pll source clock choose have issue. We update macro to get the div and freq of pll p q r by using inforamtion in pll out line Signed-off-by: Duy Nguyen <[email protected]>
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@soburi , @thaoluonguw , @KhiemNguyenT , please check this PR, this one fix issue for PLL P R Q R configuration in RA8 devices |
thaoluonguw
approved these changes
Oct 17, 2024
KhiemNguyenT
approved these changes
Oct 17, 2024
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@soburi , @thaoluonguw , @KhiemNguyenT Sorry for the late response. One consideration, PLLP, Q, R freq are derivered from PLL frequency. |
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The new update of dts in device tree make pll source clock choose have issue.
We update macro to get the div and freq of pll p q r by using inforamtion in pll out line